CAT34TS02
http://onsemi.com
11
SLAVE
ADDRESS
SDA LINE
BYTE
ADDRESS (n)
DATA n
SLAVE
ADDRESS
SLAVE
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
DATA (MSB)
SLAVE
SLAVE
DATA (LSB)
REGISTER
ADDRESS
ADDRESS
S
S
T
A
R
T
A
C
K
A
C
K
S
S
T
A
R
T
A
C
K
N
O
A
C
K
S
T
O
P
P
S
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
S
T
A
R
T
A
C
K
N
O
A
C
K
S
T
O
P
P
SPD
TS
Figure 29a. EEPROM Selective Read
Figure 29b. Temperature Sensor Selective Read
Figure 30. EEPROM Sequential Read
MASTER
SDA LINE
SLAVE
ADDRESS
SPD
SLAVE
DATA n
DATA n+1
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
S
T
O
P
P
DATA n+2
DATA n+x
Software Write Protection
The lower half of memory (first 128 bytes) can be
protected against Write requests by setting one of two
Software Write Protection (SWP) flags.
The Permanent Software Write Protection (PSWP) ag
can be set or read while all address pins are at regular CMOS
levels (GND or V
CC
), whereas the very high voltage V
HV
must be present on address pin A0 to set, clear or read the
Reversible Software Write Protection (RSWP) ag. The
D.C. OPERATING CONDITIONS for RSWP operations
are shown in Table 7.
The SWP commands are listed in Table 8. All commands
are preceded by a START and terminated with a STOP,
following the ACK or NoACK from the CAT34TS02. All
SWP related Slave addresses use the preamble: 0110 (6h),
instead of the regular 1010 (Ah) used for memory access.
For PSWP commands, the three address pins can be at any
logic level, whereas for RSWP commands the address pins
must be at preassigned logic levels.
V
HV
is interpreted as logic 1. The V
HV
condition must
be established on pin A0 before the START and
maintained just beyond the STOP. Otherwise an RSWP
request could be interpreted by the CAT34TS02 as a
PSWP request.
The SWP Slave addresses follow the standard I
2
C
convention, i.e. to read the state of the SWP ag, the LSB of
the Slave address must be 1, and to set or clear a ag, it
must be 0. For Write commands a dummy byte address and
dummy data byte must be provided (Figure 31). In contrast
to a regular memory Read, a SWP Read does not return data.
Instead the CAT34TS02 will respond with NoACK if the
ag is set and with ACK if the ag is not set. Therefore, the
Master can immediately follow up with a STOP, as there is
no meaningful data following the ACK interval (Figure 32).
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